G2 AES Core - Xilinx Edition

The XE edition of the Algotronix G2 AES Core is packaged for the Xilinx ISE tools and supports all recent families of Xilinx FPGAs

The AES-G2-XE core shares the same code base as the AES G2 Platinum edition but targets only Xilinx FPGAs. It provides the same features as the Platinum edition of the core at lower cost.

For convenience, the Xilinx Edition of the AES core is supplied as an 'active' project directory for the latest edition of the Xilinx ISE tools to allow users to get started with the core and run synthesis and pre and post-layout simulation using the supplied testbench immediately. The core source files can also be downloaded as a separate ZIP file.

Algotronix also supplies a 'Getting Started' application note which demonstrates the core running on the Xilinx Spartan 3 evaluation board. The Spartan evaluation board is not supplied with the core but can be purchased at low cost from the Xilinx online store HW-SPAR3-CPLD-DK.

To purchase or evaluate the Algotronix AES Core please e-mail cores@algotronix.com requesting the appropriate license from the table below.

AES Core G2 - Xilinx Edition
	Algotronix is a member of the Xilinx Alliance Program.
	This core is available under the Xilinx Sign Once License.
Deliverables	VHDL Source Code or compiled netlist with optimisations for Xilinx FPGAs only. Implementation directory for Xilinx tools.  The VHDL version of the core is highly flexible and can be easily configured by the user through VHDL generic parameters. Comprehensive testbench implements full AESAVS test suite.
Cipher Function	Encryptor, Decryptor or combined Encryptor/Decryptor
Cipher Modes	All modes in FIPS SP800-38A : ECB, CBC, CFB, OFB, CTR
Key Length	All standard lengths: 128, 192 or 256 bits.
Technical Information	Xilinx Edition Datasheet download (PDF 52.0kB)
Source Code License
Terms	Parameterisable VHDL Source Code. Unlimited FPGAs/ASICs Configured. Design-in support for one project from the development team. One year access to web based technical documentation and updates.
Netlist Licence
Terms	Fixed compiled netlist for one configuration of the core. Unlimited FPGAs/ASICs Configured. Design-in support for one project from core development team. One year access to web based technical documentation and updates.
Evaluation License
Terms	60 day trial, all copies of core and testbench must be deleted after 60 days if not purchased. Site License, Unlimited Projects, Maximum 5 FPGAs configured with core at any time. License must be signed by an authorised officer of the company or organisation. Not available to individuals.
Pricing	Free of Charge, except for countries where an export licence is required. Where an export licence is required to supply the core we will make a charge to cover the administrative overhead involved. This charge will be deducted from the core price if the customer decides to purchase.