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The AES-GCM core is supplied as a complete package of VHDL source code which in conjunction with the AES-G3 core implements the Galois Counter Mode of AES. Data path width is configurable and parallel AES encryptors can be provided allowing a flexible tradeoff of area against performance from around 100Mbit/sec up to 10Gbit sec on modern FPGAs.
To achieve 10Gbit/sec performance on minimum sized packets additional optimisations are required which are provided by the AES-GCM10G core.
AES GCM combines AES in counter mode with a 128 bit Galois field multiplier to provide both encryption and authentication for high speed data streams. AES-GCM is parallelisable unlike the authethicated modes of AES based on the CBC-MAC algorithm.
The GCM mode is particularly suitable for multi-gigabit networking applications and is specified in draft IEEE standard 802.1ae, IETF RFC 4106 and draft NIST SP800-38D.
To purchase or evaluate the Algotronix AES-GCM Core please e-mail cores@algotronix.com requesting the appropriate license from the table below.
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AES-GCM Core
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| Deliverables |
Complete VHDL source code package. The VHDL version of the core is highly flexible and can be easily configured by the user through VHDL generic parameters. Comprehensive testbench implements all vectors from the GCM proposal and additional vectors generated using a software implementation of AES-GCM. The test bench from the AES-G3 product can be used to fully test the AES functionality. |
| Cipher Function |
Encryptor, Decryptor or combined Encryptor/Decryptor |
| Cipher Modes |
AES-GCM |
| Key Length |
128, 192 and 256 bit |
| Technical Information |
Product Brief. Full Data sheet supplied on request to qualified customers by e-mailing cores@algotronix.com |
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Project Source Code License
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| Terms |
Parameterisable VHDL Source Code. Unlimited FPGAs/ASICs Configured. Design-in support for one project from the development team. One year access to web based technical documentation and updates. |
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Evaluation License
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| Terms |
60 day trial, all copies of core and testbench must be deleted after 60 days if not purchased. Site License, Unlimited Projects, Maximum 5 FPGAs configured with core at any time. License must be signed by an authorised officer of the company or organisation. Evaluation licences are provided at Algotronix' discretion. Not available to individuals. |
| Pricing |
Free of Charge. |
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